application note j.nicolai a AN590 / 03,93 pwm generation with st62 auto-reload timer figure 1. auto-reload timer block diagram introduction this note presents how to use the st62 auto-reload timer (artimer) for the generation of a pwm signal tunable in frequency and duty cycle. as example, the generation of a 30khz pwm signal with duty cycle proportional to an analog input voltage is presented. auto-reload timer description this timer is an 8 bit timer/counter with prescaler. it includes auto-reload pwm, capture and compare ca- pability with one input and one output pins. it is controlled by the following registers (8 bit): - mode control register (mc) - status registers (sc0, sc1) - load register (lr) - incremental counter register (tc) - compare register (cp) - reload/capture register (rc) it can also wake the mcu from wait mode and exit from stop mode if an external event is present on the input pin. the prescaler ratio can be programmed to choose the timer input frequency f in (see table 1). 1/6
pulse width modulation (pwm) generation using the pwm generation capability of the ar- timer, the cpu of the microcontroller has only to start/stop the timer and update the duty cycle. high speed pwm signals in the range of 100khz can be generated. the timer clock input frequency f in can be selected by the oscillator clock f osc and the prescaler ratio. the pwm signal period is con- trolled by the reload register. the duty cycle is de- fined by the compare register cp (see figure 2). the register tc is incremented from rc to 255d, then reloaded at rc to count again. the pwm out- put is set on the overflow of tc and reset when tc=cp. cp can have any value between rc and 255d. so rc should be minimal and the prescaler ratio as small as possible to achieve a maximum resolution. major formulae for pwm generation are: f in = f osc / (prescaler ratio) f pwm = f in / (255 - rc) duty cycle: (cp -rc) / (255 - rc) resolution: 1 / (255 - rc) with a 8mhz oscillator and a prescaler ratio of 1, the maximum resolution (1/255) leads to a pwm frequency f pwm of 31.3khz. a resolution of 1/64 al- lows to increase f pwm to 125khz. figure 2. pwm timer operation bit 0 reg. sc1 ps2 ps1 ps0 prescaler ratio 0 000 1 0 001 2 0 010 4 0 011 8 0 100 16 0 101 32 0 110 64 0 111 128 1 000 3 1 001 6 1 010 12 1 011 24 1 100 48 1 101 96 1 110 192 1 111 384 table 1. prescaler programming ratio a pwm generation with artimer 2/6
example 1: target: generate a 12khz pwm signal with a duty cycle of 37%, using an oscillator frequency of 4mhz: we want to generate a periodic signal at a frequency of 12 khz and a duty cycle of 37% . the cpu frequency (quartz frequency) is 4 mhz. lets try with a prescaler ratio of 3: f in = 4 mhz / 3 = 1333.33 khz 12 khz = 1333.33 khz / (255d - rc) gives rc = 143.889, rounded to 144 resolution = 1 /(255 - 144) = 1 / 111 duty cycle desired: 37% 0.37 = (cp - 144) / (255 - 144) yields cp = 185.07, rounded to 185. summary: prescaler = 3, rc = 144d, cp = 185d: these numbers yield a pwm frequency of 12.012 khz, a duty cycle of 36.94 % and a resolution of 0.9 %, which is very close to the initial goal. program example: - sc0 is not programmed, so it keeps its reset value 00h (all flags cleared) - the pwm signal starts as soon as the last instruction ( ldi mc ) is executed ;**************** a-r timer register set ******************* rc .def 0d9h,0ffh,0ffh ;reload/capture register cp .def 0dah,0ffh,0ffh ;compare register mc .def 0d5h,0ffh,0ffh ;mode control register sc0 .def 0d6h,0ffh,0ffh ;status/control register 0 sc1 .def 0d7h,0ffh,0ffh ;status/control register 1 lr .def 0dbh,0ffh,0ffh ;load register ;============================================================ ldi cp, 185 ;compare register = 185d ldi rc, 144 ;reload register = 144d ldi sc1,001h ;clock source= cpu clock divided by 3 ;prescaler ratio = 1 ldi mc, 11100000b ;auto-reload mode,interrupts disabled ;pwmout enabled, start timer program example a pwm generation with artimer 3/6
example 2: target: generate a pwm signal of frequency 31.3 khz with a duty cycle proportional to an input analog voltage varying between 0v and v cc : 0v corresponds to 0% duty cycle, v cc corresponds to 100% duty cycle. the cpu clock is 8 mhz: referring to example 1, we find that the prescaler ratio must be 1, the value in rc must be 0 and the value in cp is taken directly from the a/d output (varying from 0 to 255d depending upon the analog input): rc = 0 cp = 0...255d prescaler ratio = 1 f in = 8 mhz f pwm = 8 mhz / 255 = 31.37 khz duty cycle = cp / 255d resolution = 1/255d = 0.39 % we need to implement a software loop which repetitively converts the analog input to a digital value and copies this digital value into cp: a .def 0ffh,0ffh,0ffh ;accumulator ;************** port register set *************************** pa .def 0c0h,0ffh,0ffh ;data register port a padir .def 0c4h,0ffh,0ffh ;data direction reg. port a paopt .def 0cch,0ffh,0ffh ;option register port a ;**************** timer register set *********************** rc .def 0d9h,0ffh,0ffh ;reload capture register cp .def 0dah,0ffh,0ffh ;compare register mc .def 0d5h,0ffh,0ffh ;mode control register sc0 .def 0d6h,0ffh,0ffh ;status control register 0 sc1 .def 0d7h,0ffh,0ffh ;status control register 1 lr .def 0dbh,0ffh,0ffh ;load register ;**************** adc register set ************************** adcc .def 0d1h,0ffh,0ffh ;adc control register adc .def 0d0h,0ffh,0ffh ;adc result register ;************* main ***************************************** ;port a must be an iop3 type (port with analog input mode): ldi padir, 000h ldi paopt, 001h ;pa0 is the analog input ldi pa, 001h ;pa1..pa7 are input with pull-up ldi sc1,00000000b ;psc divides by 1 ldi cp,07fh ;compare register = 127d ;(initial duty = 50%) ldi rc,000h ;reload register = 0 ;(count up from 0 to 255) ldi mc,11100000b ;auto-reload mode,interrupt disabled ;pwmout enabled, start timer with ;duty cycle 50% at start-up adc_loop ldi adcc,030h ;start a/d conversion wt_eoc jrr 6,adcc,wt_eoc ;wait for end-of-conversion ld a,adc ;save result into accumulator ld cp,a ;copy it into cp reg ister jp adc_loop ;do it again program example a pwm generation with artimer 4/6
the length of the loop adc_loop is the interval at which the duty cycle of the pwm signal will be updated. in this example, this loop lasts around 76 m s, so the pwm duty cycle is updated every 2 or 3 pwm cycles. calculation of the 80 m s: - instructions ldi , ld and jp last 4 cycles of 13 clock periods -> 4 x 4 x 13 8mhz periods = 26 m s - instruction jrr lasts as long as the a/d takes to convert, which is around 50 m s at 8mhz -> total length of adc_loop at 8 mhz = approx. 76 m s this last example shows that, as requested, the cpu is not used to generate the pwm signal, but only to start/stop it and to update the duty cycle. a pwm generation with artimer 5/6
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